File : s-bbsle3.ads


   1 ------------------------------------------------------------------------------
   2 --                                                                          --
   3 --                  GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS                --
   4 --                                                                          --
   5 --       S Y S T E M . B B . B O A R D _ S U P P O R T . L E O N _ 3        --
   6 --                                                                          --
   7 --                                  S p e c                                 --
   8 --                                                                          --
   9 --        Copyright (C) 1999-2002 Universidad Politecnica de Madrid         --
  10 --             Copyright (C) 2003-2006 The European Space Agency            --
  11 --                     Copyright (C) 2003-2016, AdaCore                     --
  12 --                                                                          --
  13 -- GNARL is free software; you can  redistribute it  and/or modify it under --
  14 -- terms of the  GNU General Public License as published  by the Free Soft- --
  15 -- ware  Foundation;  either version 3,  or (at your option) any later ver- --
  16 -- sion. GNARL is distributed in the hope that it will be useful, but WITH- --
  17 -- OUT ANY WARRANTY;  without even the  implied warranty of MERCHANTABILITY --
  18 -- or FITNESS FOR A PARTICULAR PURPOSE.                                     --
  19 --                                                                          --
  20 --                                                                          --
  21 --                                                                          --
  22 --                                                                          --
  23 --                                                                          --
  24 -- You should have received a copy of the GNU General Public License and    --
  25 -- a copy of the GCC Runtime Library Exception along with this program;     --
  26 -- see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see    --
  27 -- <http://www.gnu.org/licenses/>.                                          --
  28 --                                                                          --
  29 -- GNARL was developed by the GNARL team at Florida State University.       --
  30 -- Extensive contributions were provided by Ada Core Technologies, Inc.     --
  31 --                                                                          --
  32 -- The port of GNARL to bare board targets was initially developed by the   --
  33 -- Real-Time Systems Group at the Technical University of Madrid.           --
  34 --                                                                          --
  35 ------------------------------------------------------------------------------
  36 
  37 --  This package provides the appropriate mapping for the system registers.
  38 --  This is a LEON3 specific  package, based on the UT699 LEON 3FT/SPARC V8
  39 --  Micro-Processor Advanced Users Manual, dated March 2, 2009 from
  40 --  www.aeroflex.com/LEON, referenced hereafter as AUM.
  41 
  42 --  This package is not named Leon3, as that would cause a name krunching
  43 --  collision with System.BB.Board_Support.Leon.
  44 
  45 pragma Restrictions (No_Elaboration_Code);
  46 
  47 with System.Multiprocessors;
  48 with System.BB.Parameters;
  49 with System.BB.Board_Parameters;
  50 
  51 package System.BB.Board_Support.LEON_3 is
  52    pragma Preelaborate;
  53 
  54    --  Pragma Suppress_Initialization (register_type) must be used in order
  55    --  to keep eficiency. Otherwise, initialization procedures are always
  56    --  generated for objects of packed boolean array types and of record types
  57    --  that have components of these types.
  58 
  59    ----------------------------
  60    -- Local type definitions --
  61    ----------------------------
  62 
  63    type Scaler_10 is mod 2 **  10;
  64    for Scaler_10'Size use  10;
  65    --  10-bit scaler
  66 
  67    type Scaler_12 is mod 2 **  12;
  68    for Scaler_12'Size use  12;
  69    --  12-bit scaler
  70 
  71    type Reserved_2 is array (0 .. 1) of Boolean;
  72    for Reserved_2'Size use 2;
  73    pragma Pack (Reserved_2);
  74 
  75    type Reserved_3 is array (0 .. 2) of Boolean;
  76    for Reserved_3'Size use 3;
  77    pragma Pack (Reserved_3);
  78 
  79    type Reserved_8 is array (0 .. 7) of Boolean;
  80    for Reserved_8'Size use 8;
  81    pragma Pack (Reserved_8);
  82 
  83    type Reserved_16 is array (0 .. 15) of Boolean;
  84    for Reserved_16'Size use 16;
  85    pragma Pack (Reserved_16);
  86 
  87    type Reserved_20 is array (0 .. 19) of Boolean;
  88    for Reserved_20'Size use 20;
  89    pragma Pack (Reserved_20);
  90 
  91    type Reserved_21 is array (0 .. 20) of Boolean;
  92    for Reserved_21'Size use 21;
  93    pragma Pack (Reserved_21);
  94 
  95    type Reserved_22 is array (0 .. 21) of Boolean;
  96    for Reserved_22'Size use 22;
  97    pragma Pack (Reserved_22);
  98 
  99    type Reserved_23 is array (0 .. 22) of Boolean;
 100    for Reserved_23'Size use 23;
 101    pragma Pack (Reserved_23);
 102 
 103    type Reserved_24 is array (0 .. 23) of Boolean;
 104    for Reserved_24'Size use 24;
 105    pragma Pack (Reserved_24);
 106 
 107    type Reserved_25 is array (0 .. 24) of Boolean;
 108    for Reserved_25'Size use 25;
 109    pragma Pack (Reserved_25);
 110 
 111    type Reserved_27 is array (0 .. 26) of Boolean;
 112    for Reserved_27'Size use 27;
 113    pragma Pack (Reserved_27);
 114 
 115    --  Mapping between bits in a 32-bit register as used in the hardware
 116    --  documentation and bit order as used by Ada.
 117 
 118    --  This makes it easier to verify correctness against the AUM. Ranges will
 119    --  need to be reversed, but the compiler will check this.
 120 
 121    Bit00 : constant := 31; Bit01 : constant := 30; Bit02 : constant := 29;
 122    Bit03 : constant := 28; Bit04 : constant := 27; Bit05 : constant := 26;
 123    Bit06 : constant := 25; Bit07 : constant := 24; Bit08 : constant := 23;
 124    Bit09 : constant := 22; Bit10 : constant := 21; Bit11 : constant := 20;
 125    Bit12 : constant := 19; Bit13 : constant := 18; Bit14 : constant := 17;
 126    Bit15 : constant := 16; Bit16 : constant := 15; Bit17 : constant := 14;
 127    Bit18 : constant := 13; Bit19 : constant := 12; Bit20 : constant := 11;
 128    Bit21 : constant := 10; Bit22 : constant := 09; Bit23 : constant := 08;
 129    Bit24 : constant :=  7; Bit25 : constant := 06; Bit26 : constant := 05;
 130    Bit27 : constant :=  4; Bit28 : constant := 03; Bit29 : constant := 02;
 131    Bit30 : constant :=  1; Bit31 : constant := 00;
 132 
 133    ---------------------
 134    -- Timer Registers --
 135    ---------------------
 136 
 137    Timer_Base : constant := System.BB.Board_Parameters.Timer_Base;
 138 
 139    subtype Timer_Register is Timer_Interval;
 140    pragma Suppress_Initialization (Timer_Register);
 141 
 142    type Timer_Control_Register is
 143       record
 144          Enable            : Boolean;
 145          --  1  : enable counting
 146          --  0  : hold scaler (and counter) w
 147 
 148          Reload_Counter    : Boolean;
 149          --  1  : reload counter at zero and restart
 150          --  0  : stop counter at zero w
 151 
 152          Load_Counter      : Boolean;
 153          --  1  : load counter with preset value and start if enabled
 154          --  0  : no function w
 155 
 156          Interrupt_Enable  : Boolean;
 157          --  1  : timer underflow signals interrupt
 158          --  0  : interrupts disabled
 159 
 160          Interrupt_Pending : Boolean;
 161          --  0  : interrupt not pending
 162          --  1  : interrupt pending, remains 1 until writing 0 to this bit
 163 
 164          Chain             : Boolean;
 165          --  0  : timer functions independently
 166          --  1  : decrementing timer N begins when timer (N - 1) underflows
 167 
 168          Debug_Halt        : Boolean; -- State of timer when DF = 0, read only
 169          --  0  : active
 170          --  1  : frozen
 171 
 172          Reserved          : Reserved_25;
 173       end record;
 174 
 175    for Timer_Control_Register use
 176       record
 177          Reserved          at 0 range Bit31 .. Bit07;
 178          Debug_Halt        at 0 range Bit06 .. Bit06;
 179          Chain             at 0 range Bit05 .. Bit05;
 180          Interrupt_Pending at 0 range Bit04 .. Bit04;
 181          Interrupt_Enable  at 0 range Bit03 .. Bit03;
 182          Load_Counter      at 0 range Bit02 .. Bit02; -- Load_Timer (LD) in AUM
 183          Reload_Counter    at 0 range Bit01 .. Bit01; -- Restart (RS) in AUM
 184          Enable            at 0 range Bit00 .. Bit00;
 185       end record;
 186 
 187    for Timer_Control_Register'Size use 32;
 188    pragma Suppress_Initialization (Timer_Control_Register);
 189 
 190    -------------
 191    -- Timer 1 --
 192    -------------
 193 
 194    Timer_1_Counter : Timer_Register;
 195    Timer_1_Reload  : Timer_Register;
 196    Timer_1_Control : Timer_Control_Register;
 197 
 198    pragma Atomic (Timer_1_Counter);
 199    pragma Atomic (Timer_1_Reload);
 200    pragma Atomic (Timer_1_Control);
 201 
 202    for Timer_1_Counter'Address use System'To_Address (Timer_Base + 16#10#);
 203    for Timer_1_Reload'Address  use System'To_Address (Timer_Base + 16#14#);
 204    for Timer_1_Control'Address use System'To_Address (Timer_Base + 16#18#);
 205 
 206    -------------
 207    -- Timer 2 --
 208    -------------
 209 
 210    Timer_2_Counter : Timer_Register;
 211    Timer_2_Reload  : Timer_Register;
 212    Timer_2_Control : Timer_Control_Register;
 213 
 214    pragma Atomic (Timer_2_Counter);
 215    pragma Atomic (Timer_2_Reload);
 216    pragma Atomic (Timer_2_Control);
 217 
 218    for Timer_2_Counter'Address use System'To_Address (Timer_Base + 16#20#);
 219    for Timer_2_Reload'Address  use System'To_Address (Timer_Base + 16#24#);
 220    for Timer_2_Control'Address use System'To_Address (Timer_Base + 16#28#);
 221 
 222    -------------
 223    -- Timer 3 --
 224    -------------
 225 
 226    Timer_3_Counter : Timer_Register;
 227    Timer_3_Reload  : Timer_Register;
 228    Timer_3_Control : Timer_Control_Register;
 229 
 230    pragma Atomic (Timer_3_Counter);
 231    pragma Atomic (Timer_3_Reload);
 232    pragma Atomic (Timer_3_Control);
 233 
 234    for Timer_3_Counter'Address use System'To_Address (Timer_Base + 16#30#);
 235    for Timer_3_Reload'Address  use System'To_Address (Timer_Base + 16#34#);
 236    for Timer_3_Control'Address use System'To_Address (Timer_Base + 16#38#);
 237 
 238    -------------
 239    -- Timer 4 --
 240    -------------
 241 
 242    Timer_4_Counter : Timer_Register;
 243    Timer_4_Reload  : Timer_Register;
 244    Timer_4_Control : Timer_Control_Register;
 245 
 246    pragma Atomic (Timer_4_Counter);
 247    pragma Atomic (Timer_4_Reload);
 248    pragma Atomic (Timer_4_Control);
 249 
 250    for Timer_4_Counter'Address use System'To_Address (Timer_Base + 16#40#);
 251    for Timer_4_Reload'Address  use System'To_Address (Timer_Base + 16#44#);
 252    for Timer_4_Control'Address use System'To_Address (Timer_Base + 16#48#);
 253 
 254    --------------
 255    -- Watchdog --
 256    --------------
 257 
 258    --  Watchdog_Register_Address is not available.
 259    --  On LEON3, Timer_4 also drives the WDOGN watchdog signal
 260 
 261    Watchdog_Register : Timer_Register renames Timer_4_Counter;
 262 
 263    ---------------
 264    -- Prescaler --
 265    ---------------
 266 
 267    type Prescaler_Register is
 268       record
 269          Value    : Scaler_10;
 270          Reserved : Reserved_22;
 271       end record;
 272 
 273    for Prescaler_Register use
 274       record
 275          Reserved at 0 range Bit31 .. Bit10;
 276          Value    at 0 range Bit09 .. Bit00;
 277       end record;
 278 
 279    for Prescaler_Register'Size use 32;
 280 
 281    pragma Suppress_Initialization (Prescaler_Register);
 282 
 283    Prescaler_Counter : Prescaler_Register;
 284    pragma Atomic (Prescaler_Counter);
 285    for Prescaler_Counter'Address use System'To_Address (Timer_Base + 16#00#);
 286 
 287    Prescaler_Reload : Prescaler_Register;
 288    pragma Atomic (Prescaler_Reload);
 289    for Prescaler_Reload'Address use System'To_Address (Timer_Base + 16#04#);
 290 
 291    --------------------------
 292    --  Interrupt Registers --
 293    --------------------------
 294 
 295    Irqmp_Base : constant := System.BB.Board_Parameters.Irqmp_Base;
 296 
 297    type Interrupt_Register is mod 2**32;
 298    for Interrupt_Register'Size use 32;
 299    pragma Suppress_Initialization (Interrupt_Register);
 300 
 301    ------------------------------
 302    -- Interrupt Level Register --
 303    ------------------------------
 304 
 305    Interrupt_Level : Interrupt_Register;
 306    pragma Atomic (Interrupt_Level);
 307    for Interrupt_Level'Address use System'To_Address (Irqmp_Base + 16#00#);
 308 
 309    --------------------------------
 310    -- Interrupt Pending Register --
 311    --------------------------------
 312 
 313    Interrupt_Pending : Interrupt_Register;
 314    pragma Atomic (Interrupt_Pending);
 315    for Interrupt_Pending'Address use System'To_Address (Irqmp_Base + 16#04#);
 316 
 317    -------------------------------
 318    -- Interrupt Force Registers --
 319    -------------------------------
 320 
 321    --  On single CPU Leon3 (e.g. UT699), there is only one interrupt force
 322    --  register, mapped at 16#8000_0208#. On SMP Leon3, there is one interrupt
 323    --  force register for each CPU, starting at 16#8000_0280#. The register at
 324    --  16#8000_0208# is an alias to 16#8000_0280#.
 325 
 326    type Interrupt_Force_Registers is
 327      array (System.Multiprocessors.CPU) of Interrupt_Register;
 328    for Interrupt_Force_Registers'Component_Size use 32;
 329    pragma Atomic_Components (Interrupt_Force_Registers);
 330 
 331    Interrupt_Force : Interrupt_Force_Registers;
 332    for Interrupt_Force'Address use
 333      System'To_Address (if System.BB.Parameters.Multiprocessor
 334                         then Irqmp_Base + 16#80# else Irqmp_Base + 16#08#);
 335 
 336    ------------------------------
 337    -- Interrupt Clear Register --
 338    ------------------------------
 339 
 340    Interrupt_Clear : Interrupt_Register;
 341    pragma Atomic (Interrupt_Clear);
 342    for Interrupt_Clear'Address use System'To_Address (Irqmp_Base + 16#0C#);
 343 
 344    ------------------------------
 345    -- Interrupt Mask Registers --
 346    ------------------------------
 347 
 348    type Interrupt_Mask_Registers is
 349      array (System.Multiprocessors.CPU) of Interrupt_Register;
 350    for Interrupt_Mask_Registers'Component_Size use 32;
 351    pragma Atomic_Components (Interrupt_Mask_Registers);
 352 
 353    Interrupt_Mask : Interrupt_Mask_Registers;
 354    for Interrupt_Mask'Address use System'To_Address (Irqmp_Base + 16#40#);
 355 
 356    ------------------------------------
 357    -- Multiprocessor status register --
 358    ------------------------------------
 359 
 360    type Scalar_4 is mod 2**4;
 361    for Scalar_4'Size use 4;
 362 
 363    --  Bit array for CPU status. Previously this was a packed array of
 364    --  booleans, but was numbered in reverse order (as SPARC is big endian).
 365    type CPU_Status is mod 2**16;
 366    for CPU_Status'Size use 16;
 367 
 368    type Multiprocessor_Status_Register is
 369       record
 370          NCPUS : Scalar_4;
 371          --  Number of CPUs - 1
 372 
 373          Reserved : Reserved_8;
 374 
 375          EIRQ : Scalar_4;
 376          --  Interrupt number used for extended interrupts. 0 if extended
 377          --  interrupts are disabled.
 378 
 379          Status : CPU_Status;
 380          --  Power-down status of CPU [n]: 0 = power-down, 1 = running. Write
 381          --  with 1 to start processor n.
 382       end record;
 383 
 384    for Multiprocessor_Status_Register use
 385       record
 386          NCPUS    at 0 range Bit31 .. Bit28;
 387          Reserved at 0 range Bit27 .. Bit20;
 388          EIRQ     at 0 range Bit19 .. Bit16;
 389          Status   at 0 range Bit15 .. Bit00;
 390       end record;
 391 
 392    for Multiprocessor_Status_Register'Size use 32;
 393    pragma Suppress_Initialization (Multiprocessor_Status_Register);
 394 
 395    Multiprocessor_Status : Multiprocessor_Status_Register;
 396    for Multiprocessor_Status'Address use
 397        System'To_Address (Irqmp_Base + 16#10#);
 398 
 399    --------------------
 400    -- UART Registers --
 401    --------------------
 402 
 403    type FIFO_Count is mod 64;
 404    for FIFO_Count'Size use 6;
 405 
 406    type Parity_Kind is (Even, Odd);
 407 
 408    type UART_Data_Register is
 409       record
 410          FIFO : Character;
 411          --  Reading and writing accesses receiver resp. transmitter FIFOs
 412 
 413          Reserved : Reserved_24;
 414          --  Not used r
 415       end record;
 416 
 417    for UART_Data_Register use
 418       record
 419          Reserved at 0 range Bit31 .. Bit08;
 420          FIFO     at 0 range Bit07 .. Bit00;
 421       end record;
 422 
 423    type Reserved_9 is mod 2**9;
 424    for Reserved_9'Size use 9;
 425 
 426    for UART_Data_Register'Size use 32;
 427    pragma Suppress_Initialization (UART_Data_Register);
 428 
 429    type UART_Status_Register is
 430       record
 431          Data_Ready                       : Boolean;
 432          Transmitter_Shift_Register_Empty : Boolean;
 433          Transmitter_FIFO_Empty           : Boolean;
 434          Break_Received                   : Boolean;
 435          Overrun                          : Boolean;
 436          Parity_Error                     : Boolean;
 437          Framing_Error                    : Boolean;
 438          Transmitter_FIFO_Half_Full       : Boolean;
 439          Receiver_FIFO_Half_Full          : Boolean;
 440          Transmitter_FIFO_Full            : Boolean;
 441          Receiver_FIFO_Full               : Boolean;
 442          Reserved                         : Reserved_9;
 443          Transmitter_FIFO_Count           : FIFO_Count;
 444          Receiver_FIFO_Count              : FIFO_Count;
 445       end record;
 446 
 447    for UART_Status_Register use
 448       record
 449          Receiver_FIFO_Count              at 0 range Bit31 .. Bit26;
 450          Transmitter_FIFO_Count           at 0 range Bit25 .. Bit20;
 451          Reserved                         at 0 range Bit19 .. Bit11;
 452          Receiver_FIFO_Full               at 0 range Bit10 .. Bit10;
 453          Transmitter_FIFO_Full            at 0 range Bit09 .. Bit09;
 454          Receiver_FIFO_Half_Full          at 0 range Bit08 .. Bit08;
 455          Transmitter_FIFO_Half_Full       at 0 range Bit07 .. Bit07;
 456          Framing_Error                    at 0 range Bit06 .. Bit06;
 457          Parity_Error                     at 0 range Bit05 .. Bit05;
 458          Overrun                          at 0 range Bit04 .. Bit04;
 459          Break_Received                   at 0 range Bit03 .. Bit03;
 460          Transmitter_FIFO_Empty           at 0 range Bit02 .. Bit02;
 461          Transmitter_Shift_Register_Empty at 0 range Bit01 .. Bit01;
 462          Data_Ready                       at 0 range Bit00 .. Bit00;
 463       end record;
 464 
 465    for UART_Status_Register'Size use 32;
 466    pragma Suppress_Initialization (UART_Status_Register);
 467 
 468    type UART_Control_Register is
 469       record
 470          Receiver_Enable                   : Boolean;
 471          Transmitter_Enable                : Boolean; --  Transmitter enable
 472          Receiver_Interrupt_Enable         : Boolean;
 473          Transmitter_Interrupt_Enable      : Boolean;
 474          Parity_Select                     : Parity_Kind;
 475          Parity_Enable                     : Boolean;
 476          Reserved_1                        : Boolean;
 477          Loop_Back                         : Boolean;
 478          Reserved_2                        : Boolean;
 479          Receiver_FIFO_Interrupt_Enable    : Boolean;
 480          Transmitter_FIFO_Interrupt_Enable : Boolean;
 481          Reserved_3                        : Reserved_21;
 482       end record;
 483 
 484    for UART_Control_Register use
 485       record
 486          Reserved_3                        at 0 range Bit31 .. Bit11;
 487          Receiver_FIFO_Interrupt_Enable    at 0 range Bit10 .. Bit10;
 488          Transmitter_FIFO_Interrupt_Enable at 0 range Bit09 .. Bit09;
 489          Reserved_2                        at 0 range Bit08 .. Bit08;
 490          Loop_Back                         at 0 range Bit07 .. Bit07;
 491          Reserved_1                        at 0 range Bit06 .. Bit06;
 492          Parity_Enable                     at 0 range Bit05 .. Bit05;
 493          Parity_Select                     at 0 range Bit04 .. Bit04;
 494          Transmitter_Interrupt_Enable      at 0 range Bit03 .. Bit03;
 495          Receiver_Interrupt_Enable         at 0 range Bit02 .. Bit02;
 496          Transmitter_Enable                at 0 range Bit01 .. Bit01;
 497          Receiver_Enable                   at 0 range Bit00 .. Bit00;
 498       end record;
 499 
 500    for UART_Control_Register'Size use 32;
 501 
 502    pragma Suppress_Initialization (UART_Control_Register);
 503 
 504    type UART_Scaler_Register is
 505       record
 506          UART_Scaler : Scaler_12;
 507          --  1 - 4095  : Divide factor
 508          --  0  : stops the UART clock
 509 
 510          Reserved : Reserved_20;
 511       end record;
 512 
 513    for UART_Scaler_Register use
 514       record
 515          Reserved    at 0 range Bit31 .. Bit12;
 516          UART_Scaler at 0 range Bit11 .. Bit00;
 517       end record;
 518 
 519    for UART_Scaler_Register'Size use 32;
 520    pragma Suppress_Initialization (UART_Scaler_Register);
 521 
 522    ----------
 523    -- UART --
 524    ----------
 525 
 526    UART_Base : constant := System.BB.Board_Parameters.UART_Base;
 527 
 528    UART_Data : UART_Data_Register;
 529    pragma Atomic (UART_Data);
 530    for UART_Data'Address use System'To_Address (UART_Base + 16#00#);
 531 
 532    UART_Status : UART_Status_Register;
 533    pragma Atomic (UART_Status);
 534    for UART_Status'Address use System'To_Address (UART_Base + 16#04#);
 535 
 536    UART_Control : UART_Control_Register;
 537    pragma Atomic (UART_Control);
 538    for UART_Control'Address use System'To_Address (UART_Base + 16#08#);
 539 
 540    UART_Scaler : UART_Scaler_Register;
 541    pragma Atomic (UART_Scaler);
 542    for UART_Scaler'Address use System'To_Address (UART_Base + 16#0C#);
 543 
 544    ----------------------------
 545    -- Cache Control Register --
 546    ----------------------------
 547 
 548    type Status_2 is mod 2 ** 2;
 549    for Status_2'Size use 2;
 550 
 551    type Test_Bit_Status is mod 2 ** 4;
 552    for Test_Bit_Status'Size use 4;
 553 
 554    type Cache_Control_Register is
 555       record
 556          Ics       : Status_2;
 557          Dcs       : Status_2;
 558          Icf       : Boolean;
 559          Dcf       : Boolean;
 560          Dde       : Status_2;
 561          Dte       : Status_2;
 562          Ide       : Status_2;
 563          Ite       : Status_2;
 564          Dp        : Boolean;
 565          Ip        : Boolean;
 566          Ib        : Boolean;
 567          Reserved1 : Reserved_2;
 568          Ft        : Status_2;
 569          Fi        : Boolean;
 570          Fd        : Boolean;
 571          Reserved2 : Boolean;
 572          Tb        : Test_Bit_Status;
 573          Ps        : Boolean;
 574          Reserved3 : Reserved_3;
 575       end record;
 576 
 577    for Cache_Control_Register use
 578      record
 579         Reserved3  at 0 range Bit31 .. Bit29;
 580         Ps         at 0 range Bit28 .. Bit28;
 581         Tb         at 0 range Bit27 .. Bit24;
 582         Reserved2  at 0 range Bit23 .. Bit23;
 583         Fd         at 0 range Bit22 .. Bit22;
 584         Fi         at 0 range Bit21 .. Bit21;
 585         Ft         at 0 range Bit20 .. Bit19;
 586         Reserved1  at 0 range Bit18 .. Bit17;
 587         Ib         at 0 range Bit16 .. Bit16;
 588         Ip         at 0 range Bit15 .. Bit15;
 589         Dp         at 0 range Bit14 .. Bit14;
 590         Ite        at 0 range Bit13 .. Bit12;
 591         Ide        at 0 range Bit11 .. Bit10;
 592         Dte        at 0 range Bit09 .. Bit08;
 593         Dde        at 0 range Bit07 .. Bit06;
 594         Dcf        at 0 range Bit05 .. Bit05;
 595         Icf        at 0 range Bit04 .. Bit04;
 596         Dcs        at 0 range Bit03 .. Bit02;
 597         Ics        at 0 range Bit01 .. Bit00;
 598      end record;
 599 
 600    for  Cache_Control_Register'Size use 32;
 601 
 602    pragma Suppress_Initialization (Cache_Control_Register);
 603 
 604 end System.BB.Board_Support.LEON_3;