APPENDIX B

PRIVATE EYE DISPLAY CONTROLLER

ASIC SPECIFICATION

Private Eye® Display Controller Specification
Document Number 300-001-00 Revision 06 October 31, 1991

	Low power CMOS device.
	Software compatible with IBM CGA display adapter.
	Supports 25 line x 40 character and 25 line x 80 character alphanumeric modes with character attributes.
	Supports 320 x 200, 640 x 200 and 720 x 280 bitmap graphics modes.
	Supports software dowuloadable fonts.
	Built-in IBM-PC interface - external data bus driver required in some applications.
	Simple interface to most processors.
	“Shadow” mode to support multiple CGA controllers in one system.
The Private Eye Display Controller (PEDC) is a single-chip controller for Reflection Technology’s Private Eye display. The PEDC is designed to interface to the IBM-PC bus. It is also easily interfaced to other computers.

The PEDC supports three basic modes of operation: CGA graphics, text, and high-resolution graphics. The first two modes are software compatible with the IBM CGA standard.

The PEDC (RTI P/N 213-008-00) is a monolithic CMOS IC, packaged in an 84-pin PLCC. It requires only a single +5 volt supply.

In addition to the PEDC, a 256K bit (32K x 8), 100 ns SRAM containing the frame buffer is required. A 128K bit
(16K x 8), 200 ns ROM containing the character set is required to support CGA compatible alphanumeric modes.
Optionally, a 256K bit (32K x 8), 100 ns SRAM may be used, allowing software downloadable character sets. An
external data bus transceiver (74LS245) is necessary for driving high-current busses like the IBM-PC bus. The
PEDC requires a clock of up to 7.16 MHz.

The PEDC communicates with the Private Eye display through its Reflection Technology Serial Interface (RTSI) port.

The Private Eye supports two levels of display intensity; image inversion (for using the Private Eye with the left eye), blanked, and standby modes. Control of these modes is available from the PEDC.

Reflection Technology Inc. believes this information is correct and reliable. However, it is subject to change without notice. No responsibility is assumed by Reflection Technology for its use; nor for infringements of patents or other rights of third parties. This document implies no license under patents or copyrights. IBM is a trademark of International Business Machines. Incorporated. Microsoft is a trademark of Microsoft Corporation.

Copyright 0 1990 Reflection Technology Inc. All rights reserved.

Table of Contents
	1. Functional Description	2
	2. Register Map	9
	3. Register Definitions	10
	4. Signal Description	11
	5. Timing Diagrams	13
	6. Electrical Specifications	15
	Appendix A. Package Description	17
	Appendix B. Character Generator Format	18
	Appendix C. Initialization Sequences	19
	Appendix D. Bugs	21

la Functional Description
This description is not intended to completely describe the IBM CGA display, nor the IBMPC bus. Suggested readings include:

Programmer’s Guide to PC & PS/2 Video Systems, Richard Wilton, Microsoft Press. ISBN 1-55615-103-9.

Interfacing to the IBM Personal Computer, Lewis Eggebrecht, Howard W. Sams & Co. ISBN 0-672-22027-X.

Notation:	/ before a signal name indicates that the signal is active low. FFH indicates a hexadecimal number.
X in a bit definition table means “don’t care”.
“Asserted” means “driven to its active level”, so a grounded active low signal
is asserted.

1.1 CGA Modes

The PEDC emulates a CGA display as closely as possible. All readable CGA registers are supported. All writable registers that affect the displayed image (except for the Color Register) are supported. The write-only CRTC registers that affect the timing of the standard CGA video signal are not supported; writing to them has no effect. The light pen registers are supported to the extent necessary to accommodate existing CGA software.

Horizontal and vertical retrace pulses are supported in the CRT Status Register to simulate a CGA display operating at 60Hz. This is for compatibility with CGA software that attempts to avoid displaying “snow” by writing to the screen during horizontal and vertical retrace.

The Mode Control Register is used to select a CGA Mode (see Appendix D #1, #4). Bit 3 of the Mode Control Register, when set to zero, blanks the display. This is done by transmitting a RTSI header with the Display Enable bit reset. This does not affect the contents of the RTSI Command Register.

1.1.1 Graphics Modes

	320h x 200v pixels, 2 bits/pixel - this mode uses two horizontal Private Eye pixels to display each image pixel. A 2 x 2 pattern is used to simulate the display of four colors.
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The table below shows the correspondence between bit patterns in display memory and the image on the Private Eye display
Eye Bit Pattern

00	Display Pattern All black	
01	75% density	
10	50% density	
11	Allred	

	640h x 200v pixels, 1 bit/pixel

Both of these graphics modes display the image in the center 640h x 200v area of the Private Eye’s 720h x 280v screen.

The display memory is interleaved in these modes to be compatible with the CGA display.

1.1.2 Text Modes
	40h x 25v characters - this mode uses two horizontal Private Eye pixels to display each
	character pixel
	80h x 25v characters

These modes use the full 720h x 280v area of the Private Eye screen. The character matrix is 9h x liv, rather than the 8h x 8v matrix used in the CGA display. This significantly improves the readability of characters, while maintaining CGA compatibility. A 256 character IBM font, created specifically for the Private Eye by Bitstream, Inc., is available from Reflection Technology Inc. for the character ROM. It is not necessary to install a character generator if the text modes are not used.

The PEDC does not display the “snows’ that is displayed on the IBM CGA text mode display when the processor writes to the display during refresh.

1.1.2.1	Character Attributes

Each character is represented in display memory by a 16-bit word: the low order byte contains the ASCII value of the character, the high order byte contains the attributes. The displayed attributes of each character on the screen can be individually controlled.

The character attributes are: normal, bold, underline, reverse video, and flashing (1 Hz) (see Appendix D, #6). The table below shows the correspondence between attribute settings and character appearance. F denotes flashing when set, and B denotes bold when set. Any bit pattern not indicated in the table will be displayed as Normal.

bit									
7	6	5	4	3	2	1	0	Style	
F	0	0	0	X	0	0	0	Allblack	
F	0	0	0	B	0	0	1	Underline	
F	0	0	0	B	1	1	1	Normal	
F	1	1	1	B	0	0	0	ReverseVideo	
F	1	1	1	X	1	1	1	AllRed	

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Characters with the Underline attribute will be displayed with all pixels set in the next-to-last row of the character. For strict CGA compatibility, the PEDC’s default is to disable Underline mode. Characters with the Underline attribute are displayed as Normal when Underline mode is disabled. Underline mode is enabled by setting the Underline Mode Enable bit in the Extended Mode Register. The flashing attribute is enabled by setting the Enable Flashing Attribute bit in the Mode Control Register. The IBM BIOS always sets the Enable Flashing Attribute bit.

1.1.2.2 Cursor

The PEDC supports a cursor in the alphanumeric modes, shown as a block of red on the character cell. It is of variable height, extending to the right and left edges of the character cell. The top and bottom of the cursor block are set by writing values to the lower five bits of the Cursor Start and Cursor End Registers. The top line is 0; the bottom line is 7.

If the value written to the low four bits of the Cursor End register is greater than 7, the cursor is displayed as if the Cursor End Register had been set to seven.

Since the Private Eye’s character cell is 11 pixels tall, the values stored in the Cursor Start and Cursor End registers are mapped to appropriate values so that the cursor’s appearance is similar to what would be displayed on a normal CGA display.

The cursor is placed on a specific character block by writing the offset of the character, relative to the start of the video buffer, to the Cursor Location Registers (see Appendix D, #3).

The visibility of the cursor is set by writing to bits 5 and 6 of the Cursor Start Register. The visibility modes are: invisible, slow blink and fast blink (see Appendix D, #8).

The cursor can be made invisible by: placing the cursor at a position that is not on the screen, or by setting the Cursor Start register to a value greater than 7, or by setting the Cursor Start Register to a value greater than that of the Cursor End register.

1.1.2.3	Downloadable Fonts

It is possible to substitute a 256K bit (32K x 8), 100 ns SRAM for the character generator ROM. To download a font into the RAM, set the Character Generator Access bit in the Extended Mode Register. This maps the character generator RAM into the frame buffer address space. The format of the RAM character generator is described in Section 8, “Character Generator Format”.

1.1.2.4 Display Memory

There are 16K bytes of display memory available in the text modes. 4000 bytes are displayed on the screen at one time in 80 character mode; 2000 bytes in 40 character mode. To set the starting address of the displayed characters on the screen, write the word offset to the CRTC Start Address Registers (see Appendix D, #2).

It is possible to read and write characters into any part of the display memory, whether or not the part that is accessed is displayed at the time. This allows one to format a screen of text while another is displayed, so that the new screen of text can be displayed instantly by changing the Start Address Registers.

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Horizontal High Resolution Mode Screen Format
1.2 High-Resolution Graphics Modes

	720h x 280v, horizontally oriented, non-interlaced bitmap. This mode’s memory format is that of a traditional raster display. See the figure below. This mode is enabled by:
clearing the extended mode register, writing 21H to the CRTC Start Address High Register, writing 98H to the CRTC Start Address Low Register, clearing and then writing 1EH to the Mode Control Register, and setting the High Resolution Mode Enable bit in the Extended Mode Register. See Appendix C for the initialization sequence.

	720h x 280v, vertically oriented bitmap (not operational; see Appendix D, #11). The figure below illustrates the format. In this mode, the PEDC keeps track of the processor’s writes to the display memory, and uses the partial update feature of RTSI to minimize the amount of data transmitted to the Private Eye to maintain the screen image. The Private Eye display system’s lowest power consumption is in this mode. This mode is enabled by setting the Vertical Mode Enable bit in the Extended Mode Register.

Vertical High Resolution Mode Screen Format

These graphics modes display the first 25200 bytes of the frame buffer memory on the full area of the Private Eye display. Each bit in the display memory corresponds to one pixel on the Private Eye display. A ‘1’ bit is displayed as a red (illuminated) pixel, and a ‘0’ bit is displayed as a black (dark) pixel.

Note that in order to go to a CGA Mode from an Extended Mode, it is necessary to reset the Extended Mode bits in the Extended Mode Register.

1.3	RTSI Interface

The PEDC communicates with the Private Eye display through the RTSI interface, defined in the document, “Reflection Technology Serial Interface Specification”. All aspects of the RTSI interface are handled automatically by the PEDC. The RTSI clock runs at the speed of the CLOCK input

The PEDC updates the Private Eye display in the following manner (except in vertical mode; see below): A refresh event is triggered when the host processor writes a byte to the display memory, or if the cursor is visible and changes state. A full screen transfer to the Private Eye is started on a refresh event. If there is another refresh event after the first transfer has started, a second transfer will be started when the first is finished.

In vertical mode the PEDC, to conserve power, transfers data in 1024 byte blocks when data is written to the display memory. If a new byte is written to the display memory by the processor, only the 1024 byte block containing it is sent to the Private Eye. The testing and transmitting of blocks is done on a round-robin basis.

For testing purposes, there is a bit in the Extended Mode Register called “Constant Update Mode Enable”. When this bit is set, full screens are sent continuously to the Private Eye display, rather than only when the display memory is written to by the processor.

When the processor writes to any portion of the display memory in text mode, the PEDC

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does not detect whether or not that portion is displayed on the screen; it always retransmits the entire screen to the Private Eye. If the displayed portion is unchanged, the displayed image is not affected.

The Private Eye’s /READY signal (active low) can be read in bit 4 of the CRT Status
Register.
The bits in the RTSI Command Register are defined in the RTSI Specification, and are all

active high.

1.4	Processor Interface

All registers are set to zero on reset, except the Mode Control Register, which is set to 0 1H.

The PEDC handles processor read/write operations to the display memory. Arbitration allows CPU accesses to display memory during transfer periods. On read cycles, the IOCHRDY signal is de-asserted by the PEDC until the read data is present on the bus. On write cycles, IOCHRDY is de-asserted until it is acceptable for the processor to de-assert the write control signal. The IOCHRDY signal is de-asserted as soon as possible after the memory cycle is initiated.

The AEN signal is asserted by the IBM-PC during DMA transfers. When asserted, the PEDC does not respond to register accesses. The PEDC supports read and write DMA transfers on the IBM-PC bus.

When an external data bus driver is necessary, the /SYSBUFEN output from the PEDC should be connected to its active low output enable. The external driver’s direction signal should be driven by:
/(SMEMR + (IOR (dot)

To access the PEDC registers: put the register number on the address lines A3-AO. If
PCMODE is asserted (see Appendix D, #5), put the address Ox3D on the address lines
Al 1-A4. If PCMODE is not asserted, assert the TOSEL signal.

To read a register, assert IOR, wait for IOCHRDY to be dc-asserted, then asserted. At this point, the PEDC’s data bus contains the data to be read. After reading the data, dc-assert
IOR.

To write a register, put the desired data on the data bus, and assert IOW for at least tiwp.

To access the PEDC display memory: put the memory address on lines A14-AO. If PCMODE is asserted, put the address OxB8 on lines A19-A15. If PCMODE is not asserted, assert the MEMSEL signal.

To read the display memory, assert SMEMR, wait for IOCHRDY to be dc-asserted, then asserted. At this point the PEDC’s data bus contains the data to be read. After reading the data, dc-assert SMEMR..

To write the display memory: put the desired data on the data bus, assert SMEMW, wait for IOCHRDY to be de-asserted, then asserted. Dc-assert SMEMW to finish the cycle.

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Vertical High Resolution Mode Screen Format

These graphics modes display the first 25200 bytes of the frame buffer memory on the full area of the Private Eye display. Each bit in the display memory corresponds to one pixel on the Private Eye display. A ‘1’ bit is displayed as a red (illuminated) pixel, and a ‘0’ bit is displayed as a black (dark) pixel.

Note that in order to go to a CGA Mode from an Extended Mode, it is necessary to reset the Extended Mode bits in the Extended Mode Register.

1.3	RTSI Interface

The PEDC communicates with the Private Eye display through the RTSI interface, defined in the document, “Reflection Technology Serial Interface Specification”. All aspects of the RTSI interface are handled automatically by the PEDC. The RTSI clock runs at the speed of the CLOCK input

The PEDC updates the Private Eye display in the following manner (except in vertical mode; see below): A refresh event is triggered when the host processor writes a byte to the display memory, or if the cursor is visible and changes state. A full screen transfer to the Private Eye is started on a refresh event. If there is another refresh event after the first transfer has started, a second transfer will be started when the first is finished.

In vertical mode the PEDC, to conserve power, transfers data in 1024 byte blocks when data is written to the display memory. If a new byte is written to the display memory by the processor, only the 1024 byte block containing it is sent to the Private Eye. The testing and transmitting of blocks is done on a round-robin basis.

For testing purposes, there is a bit in the Extended Mode Register called “Constant Update Mode Enable”. When this bit is set, full screens are sent continuously to the Private Eye display, rather than only when the display memory is written to by the processor.

When the processor writes to any portion of the display memory in text mode, the PEDC

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1.5	Option Signals

When the PCMODE signal on the PEDC is asserted, the PEDC decodes addresses internally to emulate a CGA display (see Appendix D, #5). When the PCMODE signal is deasserted, the internal decoders are disabled, pins A15 and Al6 become the active low select signals for the display memory and the registers, respectively, and signals present on A17, A18 and A19 are ignored.
		Register	Memory
	PCMODE	Addresses	Addresses
	asserted	0x3D0—0x3df	0xB8000—0xBFFFF
	dc-asserted	external	external

The SHADOW signal allows the PEDC to be used as a second CGA controller When asserted, the PEDC will not respond to read commands, so that it does not conflict with the primary CGA controller, but it will respond to write commands, so that the Private Eye will display the same information as the primary CGA controller. When SHADOW is asserted, the IOCHRDY signal is not driven by the PEDC, to avoid conflicting with the primary controller. This should not be a problem in most situations, because the PEDC has faster write cycles than most other CGA controllers (see Appendix D, #9). Note that CLOCK must be at a sufficient speed for this to work properly.

2. Register Map
	Register Number	Name	Read/Write
	4	CRTC Address	W
	5	 CRTC Data	R/W
	8	Mode Control	W (see Appendix D, #1, 4)
	A	 CRT Status	R
	Register Number	Read/Write
	XXX01010	     Cursor Start	  W (see Appendix D, #8)
	XXX01011	     Cursor End	  W
	XXX01100	  Start Address High	  W (see Appendix D, #2)
	XXX01101	  Start Address Low	  W
	XXX0 1110	  Cursor Location High	  R/W(see Appendix D, #3)
	1111	  Cursor Location Low	  R/W
	XXX10000	    LightPenHigh	  R
	XXX10001	    Light Pen Low	  R
	XXX11110	Extended Mode Register * R/W(see Appendix D, #11, 12)
	XXX11111	RTSI Command Register	* R/W

*	indicates PEDC- specific registers.

To access the CRTC registers, write the register number to the CRTC Address Register, then access the specified register with a read or write to the CRTC Data Register.

Writing to undefined or unimplemented registers has no effect. Undefined or unimplemented registers return FFH when read.

3. Register Definitions
CRT Status Register (Read Only)	RTSI Command Register
bit	Settings	bit
7	1	7	Left Eye Mode Enable
6	1	6	Standby Mode Enable
s	1	5	Display Blank Enable
4	/RTSI Ready	4	Low Intensity Enable
3	Simulated Vertical Sync	3	Reserved (must be 0)
2	1	2	Reserved (must be 0)
1	1	1	Reserved (must be 0)
0	Simulated Horizontal Sync	0	Reserved (must be 0)

Extended Mode Register (Read/Write)
7	Reserved (must be 0)
6	Continuous RTSI Update Mode Enable
5	Reserved (must be 0)
4	Underline Mode Enable
3	Character RAM (Downloadable Font) Access Enable
2	Reserved (must be 0)
1	Vertical Mode Enable (see Appendix D, #11)
0	Horizontal Mode Enable (see Appendix D, #12)

Mode Control Register (Write Only) (see Appendix D, #1, 4)

E denotes enable display when set to 1
F denotes enable flashing attribute when set to 1

bit
2			4		21 
X	X	F	0	E	X	0	0	40 x 25 text
X	X	F	0	E	X	0	1	80 x 25 text
X	X	X	0	E	X	1	0	320 x 200 graphics
X	X	X	1	E	X	1	0	640 x 200 graphics

Cursor Start Register (Write Only) (see Appendix D, #8)
bit 6	bit 5
X	0	Blink
0	1	Not Displayed
1	1	Blink

bits 4-0 indicate top of cursor

Cursor End Register (Write Only)

bits 4-0 indicate bottom of cursor
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4.	Signal Description

I/O: ti-state input/output
I:	input
0: output
OC:	open-collector output
SI:	Schmitt-trigger input
HCO:	high current output

All unused inputs must be tied to VDD or VSS.

4.1	Processor Interface
Name	Pin	Description
D7	35	I/O	CPU Data bus.
D6	36
D5	37
D4	38
D3	39
D2	40
Dl	41
DO	42
A19	34	I	CPU Address bus.
A18	31
A17	30
A16/IOSEL	29
A15/MEMSEL	28
A14	27
A13	26
A12	25
A11	24
AlO	23
A9	22
A8	21
A7	20
A6	19
A5	18
A4	17
A3	16
A2	15
Al	14
A0	13
/SMEMR	10	I	CPU memory read request.
/SMEMW	9	I	CPU memory write request.
/IOR	80	I	CPU register read request.
/IOW	8	I	CPU register write request.
RESET	68	I	CPU reset.
AEN	79	I	Disables register accesses when asserted.
IOCHRDY	78	OC	Dc-asserted by the PEDC to request wait states.
/REFRESH	7	I	Asserted during system DRAM refresh cycles.
/SYSBUFEN	69	0	Output enable for external bus transceiver.
CLOCK	73	I	PEDC Clock.
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4.2	RTSI Interface
RTSICLK	1	HCO	Clock, generated by the PEDC.
RTSIDATA	4	HCO	Data, generated by the PEDC.
/RTSIBOS	6	HCO	Scan control signal, generated by the PEDC.
/RTSIRDY	83	SI	Scan control signal, generated by the Private Eye.

4.3	Internal Interface
ID7	43	I/O	Internal data bus to frame buffer and character generator.
ID6	44
ID5	45
1D4	46
Id3	47
ID2	48
ID1	49
IDO	50
IA14	67	0	Internal address bus to frame buffer and character generator.
IA13	66
IA12	65
IA11	64
IA10	63
IA9	62
IA8	61
IA7	60
IA6	59
IA5	58
IA4	57
1A3	56
IA2	55
IA1	52
IA0	51
/FBCS	70	0	Chip select signal to the display memory.
/CGCS	72	0	Chip select signal to the character generator.
/IMEMW	71	0	Write Enable signal to the display memory and the
			character generator.

4.4	Option Bits
PCMODE	76	I	When asserted, the PEDC automatically decodes
			addresses corresponding to a CGA display. (see
			Appendix D, #5)
SHADOW	77	I	When asserted, the PEDC does not respond to processor
			read requests. (see Appendix D, #9)

4.5 Misc.
VDD	12,32		+5 Volts.
VSS	54,74		Signal Ground.
RESERVED	81	I	Must be pulled up to VDD.
RESERVED	2,3,5,11,33,		Do not connect.
	53,75,82,84

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5. Timing Diagrams
*	indicates signals that are used only when PCMODE is not asserted.

5.1	Memory Read Cycle

5.2	Memory Write Cycle

5.4	I/O Write Cycle

6.	Electrical Specifications
6.1	Absolute Maximum Ratings
Symbol	Characteristic	Min
Tstg	Storage Temperature	-65°C	 150°C
Vdd	Supply Voltage	-O.3V	7.OV
Vi	Input Voltage	-O.3V	Vdd + O.3V
V0	Output Voltage	-O.3V	Vdd + O.3V

Note: Stresses above those listed may cause permanent damage to the device. These are stress ratings only. Functional operation at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages.

6.2	DC Characteristics
Symbol Characteristic	Mi	Typ. Max
Topr	Operating Temperature	0°C	- 70°C
Vdd	Supply Voltage	4.75V	5.OOV 5.25V
Voh	High Level Output Voltage (Vdd = 4.75V, Iah = -6mA)*	2.4V	- -
Vol	Low Level Output Voltage (Vdd = 4.75V, Iol = 6mA)*	-	- O.4V
Voh	High Level Output Voltage (RTSI Outputs)	Vdd - O.4V
Vol	Low Level Output Voltage (RTSI Outputs)	Vss +
O.4V
Vih	High Level Input Voltage (Vdd = 5.25V)	2.OV	- -
Vil	Low Level Input Voltage (Vdd = 4.75V)	-	- O.8V
Iil	Input Leakage Current	-luA	-1uA
Idd	Power Supply Current (idle)	To Be Determined
Idd	Power Supply Current (RTSI active)	20 mA
Idd	Power Supply Current (clock stopped)	-	2 uP -

*	except RTSI outputs

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6.3	AC Characteristics
Symbol Characteristic	Min.
fclock	CLOCK frequency	DC	7.16 MHz
tcyc	CLOCK cycle period	140 ns
tch	CLOCK high period	40%
tcl	CLOCK low period	40%
tas	Address Setup	15 ns
tah	Address Hold	5 ns
tss	Select Setup	10 ns
tsh	Select Hold	5 ns
twd	Wait Delay		30 ns
tmrd	Memory Read Data Delay	139 ns + 3  tcyc
tmrh	Memory Read Data Hold	5.1 ns
tmrw	Memory Read Wait Period	10 ns + 5  tcyc
tmrp	Memory Read Pulse Width	0 ns after IOCHRDY asserted
tmwd	Memory Write Data Delay	tcyc
tmwh	Memory Write Data Hold	8 ns
tmww	Memory Write Pulse Width	10 ns + 5  tcyc
tmwp	Memory Write Wait Period	0 ns after IOCHRDY asserted
tird	I/O Read Data Delay		  40 ns
tirh	I/O Read Data Hold		  5.1 ns
tirw	I/O Read Pulse Width	20 ns + 3  tcyc
tirp	I/O Read Walt Period		10 ns + 3  tcyc
tiwd	I/O Write Data Delay	30 ns + tcyc
tiwh	I/O Write Data Hold	6 ns
tiwp	I/O Write Pulse Width	4  tcyc
tccd	Delay Between Cycles	tcyc
trst	RESET pulse width	4  tcyc

Specifications for external components:
tfbr	Display RAM Read Access	100 ns
tfbw	Display RAM Write Access	100 ns
tcrornr	Character ROM Read Access	200 ns
tcramr	Character RAM Read Access	200 ns
tcramw	Character RAM Write Access	100 ns

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Appendix B Character Generator Format
The character generator contains two fonts: the normal font, and the bold font. Each font contains 256 characters. Each character is constructed from a 9 x 11 cell contained in 32 bytes, made up of a 16 x 16 block of bits. The organization of the character in the block is shown in the figure below. The cell’s bits are set to 1 for pixels that are to be illuminated, and O for dark pixels. The bits in the unused area are ignored, although it is recommended that they be set to 0.

For the standard Private Eye font, the bottom row and left column of the cell are blank for characters that do not touch each other. Characters are 8 rows tall, with 2 rows used for descenders.

Character Generator Cell Format

The normal font occupies the first 8K bytes of the character generator, and the bold font occupies the second 8K. Each character in the font is stored in 32 consecutive bytes, and the characters are arranged in ascending order.

(OxOO value to disable underline)	0x10	0x05	CRTC Data
Set the Cursor Registers for block cursor	0x0a	0x04	CRTC Address: Cursor Start
(OxO 6 value for underline cursor)	OxO 0	0x05	CRTC Data
	OxOb	0x04	CRTC Address: Cursor End
	0x07	0x05	CRTC Data
Write 0 to the Start Address Register	OxOc	0x04	CRTC Address: Start Address High
	OxOO	0x05	CRTC Data
	OxOd	0x04	CRTC Address: Start Address Low
	OxOO	0x05	CRTC Data
Write 0 to the Cursor Location Register	OxOe	0x04	CRTC Address: Cursor Location
High
	OxOO	0x05	CRTC Data
	OxOf	0x04	CRTC Address: Cursor Location
Low
	OxOO	0x05	CRTC data
Clear the Mode Control Register	OxOO	0x08	Mode Control
Set the Mode Control Register	0x2 8	OxO 8	Mode Control

Appendix D Bugs
There are several bugs in the initial version of the PEDC chip (P/N 213-008-00 Revision 00). Many of the bugs can be fixed by installing two “bug-fix” PALs with the PEDC. Information on programming and installing the “Bug Fix” PALs is available upon request from Reflection Technology Applications Support. The bugs labeled * are fixed by the first PAL; those labeled t are fixed by the second PAL.

1. *	Clearing the Video Enable bit in the CGA Mode Control Register causes the display controller to hang. The “Bug Fix” PAL remedies this by not allowing this bit to be cleared. Alternatively; if possible, change the software so that it doesn’t clear the Video Enable bit.

2. *	Writing to the CRTC Start Address Registers hangs the Private Eye display until either the CGA Mode
Control Register is written to, or until the Private Eye display is unplugged, then plugged back in. The
“Bug Fix” PAL fixes this problem by simulating removal of the Private Eye display when the CRTC S cart
Address Registers are written to. Alternatively; if possible, change the software to always write to the
CGA Mode Control Register after writing to the CRTC Start Address Register

3. t	Intermittently; the cursor is displayed in the wrong place. When the cursor jumps to the wrong place, the contents of the Cursor Position Registers are incorrect. Do not use the Cursor Position Register to keep track of the cursor position when drawing text. If you do, the text will be jumbled on the screen.

4. t	Intermittently; when switching from CGA graphics mode to text mode or vice-versa, you may see a nearly blank screen, or a scrambled screen.

5. t	The PEDC chip does not operate when the PCMODE pin is dc-asserted. To map the PEDC chip’s display memory and registers to a different location, it is necessary to use external circuitry to decode the addresses, and present standard CGA addresses to the PEDC chip.

6.	Reverse video and flashing characters may not be displayed properly. Fix Some commercial software can be configured to use different character attributes, allowing you to avoid this problem.

7.	Some CGA compatible software attempts to blank the screen while updating its contents. You will see the screen being updated because screen blanking is not implemented.

8.	The cursor blink rate is always fast; cursor slow blink mode is not implemented.

9.	In shadow mode, incorrect characters intermittently appear on the screen in text mode, due to insufficient wait states requested by the other CGA display controller. How often this happens depends on the number of wait states. Fix: Use a slower CGA controller

10.	Microsoft Flight Simulator hangs in graphics mode if initialized for CGA display; color monitor Other programs may also exhibit this problem. Fix: Initialize for CGA display, monochrome monitor.

11. Extended Vertical Mode has several problems that render it unusable.

12.	In Extended Horizontal Mode, the contents of the RTSI Command Register are not reliably transmitted to the Private Eye display. Write the register in a loop, so that it eventually gets transmitted. You must determine empirically how many times to write the register so that it always gets through.

Revision History:

00 Initial Revision
01 Added unused pins, actual timing specs, minor changes to register specs, added bug list, changed PCMODE signal
02 Added references to bug list, wording changes, added initialization sequences
03 Changed block diagram, added typical current consumption
04 Address of Reflection Technology changed.
05 Section 1.5. PC mode asserted/de-asserted were swapped from correct terminology Many references to Appendix D bugs
added.
06 Section 1.2 was incorrect on initializing high resolution horizontal mode.

Please contact Reflection Technology Inc. if you wish to receive updated versions of this specification as they become available.

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