May 2012 Update

At present, I have taken a break from the hardware aspects of Loper – to work on “Jupiter,” a Linux-based emulator of the system’s essential aspects.  (Think QEMU.)

Jupiter is unlikely to be of any practical use to anyone but myself.  However, at some point, I will make it public, so that interested persons who do not have access to a Xilinx FPGA board can study the design.

This entry was written by Stanislav , posted on Tuesday May 08 2012 , filed under Cold Air, Computation, Hot Air, LoperOS, Progress . Bookmark the permalink . Post a comment below or leave a trackback: Trackback URL.

9 Responses to “May 2012 Update”

  • Cosman246 says:

    This sounds really, really cool. Please, tell us once you’ve got it to work

  • zadcha says:

    champagne !

  • Gareth says:

    Hi Stanislav,

    Just learned of your project – interesting stuff. Are you still working on it in your spare time?

  • Jupiter name already taken. You need to find a new name for Linux emulator. Call it Winblows. And quit writing shit about BC. Go work for the FED.

    • Stanislav says:

      Dear Frankie Bishop,

      > Jupiter name already taken.

      Yes, there is even a whole planet! And a Soviet stereo system. And about MAXINT other items.

      In general, idiots are banned here. But I have approved your comment, for the amusement of other readers. If you have a factual criticism of the Bitcoin pieces, post away. Otherwise please sink back into whatever Redditesque hellpit you came from.


  • Geo says:

    Hi Stanislav,

    Since the day i found your site, i can’t stop reading coz it’s indeed interesting and i really like your idea for the sane computer, im really eager to see this project arrive its goal, if you need any assitance im willing to help in any possible way. Currently im working here in China, abundant of affordable opptions for components, maybe this could help for the first prototype? Anyway, will keep reading your post and look forward to hear from you, thanks! God speed for the Loper System!

    • Stanislav says:

      Dear Geo,

      I have all the hardware components I could possibly need. What is lacking is just one thing: time.

      If you want to help: reverse-engineer the Xilinx Virtex 5 bitstream format, and post the results. But don’t use your real name: copyrasts have long arms and sharp teeth. Still interested?


      • geo says:

        Hi Stanislav,

        Unfortunately i have no experience with FPGA coz im only dealing with MCU’s and PC’s geeez but already had on eye to learn this stuff, just need the right project to be used as excuse, so i guess here it is :)

        Searching for what you ask me to do, does it mean that i should help to know the detailed sequence of bits for this particular FPGA? so i guess i need to buy a dev kit for this then, but may I ask why do we need to know this details? coz i thought Verilog or VHDL are enough to program this FPGA? Apologies for this noob questions, currently using my spare time to read and do research to be able to catch up you current progress :) i saw one site that he implement an asynchronous version of a RISC on a Spartan IIE, i send you the link on the other post

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